This invention relates to an electron beam plotting method suitable for production of, for example, a mask for exposure or a semiconductor integrated circuit, a method for producing plotting pattern data for use with such an electron beam plotting method, a substrate working method to which such an electron beam plotting method is applied, and an electron beam plotting apparatus.
Refinement of semiconductor integrated circuits has proceeded in a cycle of approximately 3 years. In order to refine a semiconductor integrated circuit, a pattern for a semiconductor integrated circuit (such a pattern may sometimes be referred to as circuit pattern) must be reduced in scale. Since it requires very much time to try to proceed with designing of a circuit pattern of a reduced scale again from the beginning, a method is adopted very frequently to multiply an existing design circuit pattern by a reduction ratio to reduce the scale of the entire design circuit pattern and make an amendment to each inappropriate portion of the design pattern. This method can provide a higher design efficiency of a circuit pattern. It is to be noted that the amendment to an inappropriate portion of a design circuit pattern may be, for example, where a transistor element has a property different from a desired property, an operation to increase or decrease the width of the design circuit pattern.
For formation of a circuit pattern, a mask for exposure called reticule is normally used. In order to produce a mask for exposure, plotting pattern data is produced based on a design circuit pattern. Then, based on the plotting pattern data, a pattern is plotted on a resist applied to a mask blank using an electron beam. Then, using an etching mask obtained by developing the plotted resist, the mask blank is patterned. By the process, a mask for exposure can be obtained. In a pattern plotting method which employs an electron beam, a raster scanning method or a vector scanning method is normally adopted as a scanning method for a beam, and for the shape of a beam, a variable shaping beam method or a Gaussian beam method is adopted normally. Meanwhile, in order to form a circuit pattern using a mask for exposure, an exposure apparatus of the reduction optical system is used widely. In this instance, a pattern having a size as large as k times that of a design circuit pattern is formed on the mask for exposure. It is to be noted that, in the following description, it is assumed that k=5 for convenience of description.
Also a technique for forming a circuit pattern by a so-called direct electron beam plotting method is known. In the circuit pattern formation technique just mentioned, for example, an electron beam sensitive resist is applied to a processing object layer formed on a semiconductor substrate, and a pattern is plotted on the resist using an electron beam. Then, the processing object layer is patterned using an etching mask obtained by developing the thus plotted resist.
By the way, when it is tried to multiply an existing design circuit pattern by a reduction ratio to reduce the scale of the entire design circuit pattern, a problem that a circuit pattern of an accurately reduced scale cannot be obtained sometimes occurs. For example, the width of a design circuit pattern of a reduced scale when a design circuit pattern of 0.35 .mu.m wide is reduced by 30% in scale is 0.35.times.0.7=0.245 .mu.m. The width of a pattern to be formed on a mask for exposure in order to form a design circuit pattern of the reduced scale is, where k=5, 0.245.times.5=1.225 .mu.m. On the other hand, the minimum plotting grid length of an electron beam plotting apparatus used for production of a mask for exposure is, for example, 0.05 .mu.m. Accordingly, a pattern of 1.225 .mu.m wide cannot be formed on a mask for exposure, but only a pattern of 1.20 .mu.m wide (0.24 .mu.m on a circuit pattern) or 1.25 .mu.m wide (0.25 .mu.m on a circuit pattern) can be produced on a mask for exposure. Where a pattern accurately reduced in scale cannot be formed on a mask for exposure in this manner, a large number of inappropriate portions which must be amended are produced on a design circuit pattern.
Further, for example, from a characteristic of a semiconductor integrated device, when it is tried to change the width of a design circuit pattern from 0.30 .mu.m to 0.31 .mu.m, the width of the design circuit pattern must be changed without changing the position of the center (center of gravity) of the design circuit pattern. In particular, the positions of the opposite sides of the design circuit pattern are moved outwardly by 0.005 .mu.m. It is to be noted that, if only one of the opposite sides of a design circuit pattern is moved outwardly by 0.01 .mu.m, then it is sometimes displaced from a wiring line on an upper layer, resulting in failure in contact with the wiring line. However, where it is tried to move both of the positions of the opposite sides of a design circuit pattern outwardly by 0.05 .mu.m as described above, the positions of the opposite sides of a pattern to be formed on a mask for exposure must be moved outwardly by 0.025 .mu.m. However, such processing cannot be performed because the minimum plotting grid length of an electron beam plotting apparatus used for production of a mask for exposure is, for example, 0.05 .mu.m. After all, the width of the design circuit pattern cannot be avoided to determine to be 0.32 .mu.m.
As described above, designing of a pattern of an semiconductor integrated circuit is restricted from the magnitude of a minimum plotting grid of an electron beam plotting apparatus for production of a mask for exposure, and such restriction makes a significant obstacle to formation of a desired pattern of a semiconductor integrated circuit. Although this problem can be overcome if the magnitude of a minimum plotting grid of the electron beam plotting apparatus can be made smaller (for example, if the minimum plotting grid length is reduced to 0.001 .mu.m), an electron beam plotting apparatus of the type just described is very expensive. On the other hand, where, for example, in an electron beam plotting apparatus of the raster scanning type, the magnitude of a minimum plotting grid is reduced to raise the resolution, this gives rise to another problem that an excessively long plotting time is required unless a high blanking frequency is used.
Meanwhile, where, in an electron beam plotting apparatus of the vector scanning type, the magnitude of a minimum plotting grid is reduced, not only is it required to deflect an electron beam accurately in a unit smaller than that of a ordinary electron beam plotting apparatus, but also the position of a stage on which a mask blank is placed must be controlled accurately to cause an electron beam to collide accurately at a desired position of the mask blank. To this end, also the resolution of a detector such as a laser interferometer must be raised accordingly.
Furthermore, if effective figures of plotting pattern data are increased, the size of plotting pattern data may become excessively large, and the amount of plotting pattern data which can be set at a time to the electron beam plotting apparatus is limited. As a result, there is the possibility that plotting pattern data to be used for production of a plurality of masks for exposure may not be set at a time to the electron beam plotting apparatus.
As described above, various difficulties are involved in reduction of the magnitude of a minimum plotting grid of an electron beam plotting apparatus.